Mechanical stresses within a semiconductor device substrate can be used to modulate device performance. For example, in silicon, hole mobility is enhanced when the silicon film is under compressive stress, while the electron mobility is enhanced when the silicon film is under tensile stress. Therefore, compressive and/or tensile stresses can be advantageously created in the channel regions of p-channel MOSFETs and/or n-channel MOSFETs, in order to enhance the performance of such p-channel and/or n-channel MOSFETs.
One conventional approach for creating a stressed silicon channel region is to form such a channel region upon a stress-inducing buffer layer. For example, a tensilely stressed silicon channel layer can be formed by epitaxially growing silicon over a thick, relaxed SiGe buffer layer. The lattice constant of germanium is about 4.2% greater than that of silicon, and the lattice constant of a silicon-germanium (SiGe) alloy is linear with respect to its germanium concentration. As a result, the lattice constant of a SiGe alloy with twenty atomic percent of germanium is about 0.8% greater than the lattice constant of silicon. Epitaxial growth of silicon on such a SiGe buffer layer will yield a silicon channel layer under tensile stress, with the underlying SiGe buffer layer is essentially unstrained, or “relaxed.”
Another conventional approach for creating compressive and/or tensile stresses in the channel regions of the p-MOSFET and/or n-MOSFET devices is to cover the devices with compressively and/or tensilely stressed silicon nitride films.
However, the aforementioned approaches can only provide tensile or compressive stresses ranging from about 200 MPa to about 500 MPa, which significantly limit the performance of the resulting MOSFET devices.
Therefore, there is a continuing need for structures and methods that can provide higher stresses to MOSFETs, so as to improve the performance of such MOSFETs.